Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on a specimen such as a reticle and a wafer. Inspection processes have always been an important part of fabricating semiconductor devices such as integrated circuits. However, as the dimensions of semiconductor devices decrease, inspection processes become even more important to the successful manufacture of acceptable semiconductor devices. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary since even relatively small defects may cause unwanted aberrations in the semiconductor devices.
Accordingly, much work in the inspection field has been devoted to designing inspection systems that can detect defects having sizes that were previously negligible. Typical inspection processes detect defects by comparing similar semiconductor device areas on a wafer. The differences detected between the two device areas can either be a defect, which can cause a device to function improperly, or a nuisance, which will not affect system operations. An integral phase of semiconductor wafer inspection involves optimizing the settings, commonly referred to as the “recipe,” of an inspection device so that it can accurately distinguish defects from nuisances. After potential defects are found by an inspection system, the wafer is typically transferred to a review tool for classification of the defects. However, classification of the defects requires optimizing the settings of the review tool, also referred to as a “recipe”, so that the review tool can adequately classify the potential defects or determine that the potential defects are nuisances or false defects. In sum, analysis of the defects on a particular wafer lot requires setting up and optimizing a recipe for an inspection tool and setting up a different recipe for the review tool. Setting up two recipes for two different tools is time consuming and complex.
Inspection for many different types of defects has also become more important recently. For instance, in order to use inspection results to monitor and correct semiconductor fabrication processes, it is often necessary to know what types of defects are present on a wafer. In addition, since controlling every process involved in semiconductor manufacturing is desirable to attain the highest yield possible, it is desirable to have the capability to detect the different types of defects that may result from many different semiconductor processes. The different types of defects that are to be detected may vary dramatically in their characteristics. For example, defects that may be desirable to detect during a semiconductor manufacturing process may include thickness variations, particulate defects, scratches, pattern defects such as missing pattern features or incorrectly sized pattern features, and many others having such disparate characteristics.
Defect review typically involves generating additional information about defects at a higher resolution using either a high magnification optical system or a scanning electron microscope (SEM). The higher resolution data for the defects generated by defect review is more suitable for determining attributes of the defects such as profile, roughness, more accurate size information, etc. Defect analysis may also be performed using a system such as an electron dispersive x-ray spectroscopy (EDS) system. Such defect analysis may be performed to determine information such as composition of the defects. Attributes of the defects determined by inspection, review, analysis, or some combination thereof can be used to identify the type of the defect (i.e., defect classification) and possibly a root cause of the defects. This information can then be used to monitor and alter one or more parameters of one or more semiconductor fabrication processes to reduce or eliminate the defects.
As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitations on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. Therefore, as design rules shrink, the population of potentially yield relevant defects and nuisance defects detected by inspection grows dramatically. Therefore, more and more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive. As such, determining which of the defects actually have an effect on the performance of the devices and the yield may allow process control methods to be focused on those defects while largely ignoring others. Furthermore, at smaller design rules, process induced failures may, in some cases, tend to be systematic. That is, process induced failures tend to fail at predetermined design patterns often repeated many times within the design. Elimination of spatially systematic, electrically relevant defects is important because eliminating such defects can have a significant overall impact on yield. Whether or not defects will affect device parameters and yield often cannot be determined from the inspection, review, and analysis processes described above since these processes may not be able to determine the position of the defect with respect to the electrical design